1. Field of the Invention
This invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a surface passivation layer which is indispensable for the construction of diodes and transistors having high reliability.
2. Description of the Prior Art
The surface passivation layer is generally formed by the vapor growth method. Studies have been made on the material of the surface passivation layer in order to make semiconductor elements more passive and more stable.
For example, SiO.sub.2 is most widely used as the material of the surface passivation layer. An SiO.sub.2 layer is coated on the PN junction of the diode which is exposed at the surface of a silicon semiconductor substrate. However, in operation, an undesirable memory function is induced by the positive charge existing in the SiO.sub.2 layer. A channel is formed in the P-type semiconductor substrate, due to the negative charge induced by the positive charge in the SiO.sub.2 layer. Moreover, the positive and negative charges above mentioned are fixed due to the polarization in the shielding resin. As a result, the breakdown voltage of the PN junction is lowered, and the reliability is deteriorated by external electric fields. Accordingly, the SiO.sub.2 layer has undesirable characteristics. Moreover, the surface of Si is apt to be distorted due to the difference between the coefficients of thermal expansion of the SiO.sub.2 layer and the semiconductor substrate.
In order to remove the above-mentioned disadvantages, a laminated structure will be considered in which a polycrystalline silicon layer is coated on the PN junction of the diode exposed at the surface of the silicon semiconductor substrate and the SiO.sub.2 layer is coated on the polycrystalline silicon layer. Since the resistance of the polycrystalline silicon layer is smaller than that of SiO.sub.2, no electrical charge will be induced which is in contrast to the single layer structure of SiO.sub.2 as mentioned above. Accordingly, the breakdown voltage of the PN junction can be raised. A high breakdown voltage is desired for integrated circuits. Moreover, the reliability can be improved. However, since the electrical charges in the semiconductor substrate can flow through the polycrystalline silicon layer, the laminated structure has the disadvantages that the reverse leakage current is increased, the h.sub.FE is lowered and the noise is increased.